1. Field of the Invention
This invention relates to packaged semiconductor devices. More particularly, this invention relates to a semiconductor device having semiconductor chips molded by a synthetic resin package in a state that they are interconnected with each other to enhance integration degree.
2. Description of the Prior Art
As well known, the semiconductor device generally has a semiconductor chip (IC chip) formed with circuit elements molded by a package of a thermosetting resin, such as an epoxy resin.
In a molding process for providing a package like this, a transfer-mold method is employed. The transfer-mold method involves the steps of placing a semiconductor chip in a hermetic state within a cavity of a metal mold, injecting a molten synthetic resin under high pressure into the cavity, and then cooling the synthetic resin down for curing.
In the transfer mold method, the package and/or semiconductor chip is acted upon by various stresses, involving the stress caused upon injecting a molten synthetic resin, the stress caused by contraction of synthetic resin upon solidification, and the stress caused by the difference in coefficient of thermal expansion of between the package and the semiconductor chip. Accordingly, there is a possibility that the package and the chip might suffer from damages. Besides this, there arises another problem. Specifically, the material for mold packages, i.e. a molten synthetic resin, is mixed with filler particles in order to increase its mechanical strength. The filler particles are strongly pressed on the semiconductor chip through the action of the stresses as stated above. Due to this, the filler particles are directly forced in the circuit element formed on the semiconductor chip, possibly resulting in damage to the circuit element.
It is noted that there is one method for reducing the stresses caused on a surface of the semiconductor chip due to hard filler particles contained in the package resin, as disclosed, e.g., in Japanese Laying-open Patent Publication No. H5-82679[H01L 23/29, 31] laid open to public on Apr. 2, 1993. This prior art includes process steps of covering a semiconductor chip with a polyimide resin, and thereafter molding a resin package thus formed. This prior art is effective to relieve the stresses caused by filler particles on the semiconductor chip surface, but raises a new further problem to be solved.
That is, where the surface of a semiconductor chip is covered by a polyimide resin as in Japanese Laying-open Patent Publication No. H5-82679, a resin layer after once formed has to be removed off at its bonding area by etching so as to expose the bonding area, as is shown in FIG. 3 of the same publication. That is, there is a disadvantage that this prior art involves complication in the process of manufacturing a semiconductor device.